As microchips increasingly become an integral part of our lives, share prices for many companies that make them are rising fast. Last week shares of NVIDIA Corp (NVDA) jumped over 30%, pushing its market cap over $1 trillion, following its latest earnings announcement. Its shares were up 180% year-to-date as of June 13. The iShares Semiconductor Sector ETF (SOXX) has gained more than 45% YTD, and the VanEck Semiconductor ETF (SMH) has gained over 50%. This area is getting a lot of investor attention, but it is also an industry that may be on the cusp of a revolution.
In the nearly 80 years since the first modern digital computers were built, somewhere around 700 executable computer programming languages have been created - ranging from Fortran (oh, how I loved your clarity) to Pascal (the bane of my teenage years) and C++ (getting better…) to Python (beautifully simple) -- but these languages cannot communicate directly with the processors in your laptop, mobile phone, or smartwatch. Another layer, the computer’s Instruction Set Architecture (ISA), translates the programming language into instructions that a microchip can understand. For years, this layer has been dominated by two major types: x86, the main choice of Intel (INTC) and AMD (AMD), and Arm, the product of Softbank Group’s (SFTBF) subsidiary Arm Ltd.
However, a new player has emerged in recent years, challenging the status quo and disrupting the industry's dynamics. RISC-V (pronounced “risk five”) is an open-source ISA gaining significant momentum, so much so that MIT Technology Review listed it as one of the Ten breakthrough technologies for 2023. This article will explore how RISC-V reshapes the landscape, fosters innovation, and offers new opportunities for developers, startups, and established companies.
The Birth of RISC-V
The RISC-V project (which stands for Reduced Instruction Set Computer - Version 5) began in 2010 at the University of California, Berkeley, as a teaching tool for chip design because proprietary CPUs were too complicated and opaque for students. After its creators made the instruction set public, they soon found themselves inundated by questions about it. In 2015, a group of companies - including Alphabet (GOOG) and IBM (IBM) - and academic institutions founded RISC-V International to standardize the instruction set. Today the organization is incorporated in Switzerland with over 3,100 RISC-V members across 70 countries contributing and collaborating on open specifications. Click here if you would like more about its history.
Advantages of RISC-V
1. Open-Source. Unlike proprietary ISAs such as x86 and Arm, the RISC-V instruction set is available under royalty-free open-source licenses. It is free to use, modify, and distribute, enabling anyone to design and implement processors based on this architecture without licensing restrictions. This open approach has fueled RISC-V’s rapid growth and adoption across a wide range of industries. Since it is not tied to a single vendor or controlled by a select few, RISC-V fosters competition and innovation, which drives down costs and encourages the development of specialized processors.
The open-source nature also alleviates potential legal problems in the future, such as the current fight between Qualcomm (QCOM) and ARM. Last year, following Qualcomm’s $1.4 billion acquisition of the company, Arm pulled licenses from Nuvia and then sued Qualcomm to block its use of Nuvia’s solutions, which effectively is an attempt to block Qualcomm from benefiting from its acquisition. The dispute centers around the rights to develop a chip using ARM’s ISA – a dispute that would not occur with RISC-V ISA, which is probably looking more attractive to Qualcomm these days.
High-Performance Computing Capacity is also becoming a strategic imperative for any nation’s scientific and economic progress. The kinds of restrictions being placed on China or Russia are incentivizing the adoption of RISC-V. The European Chips Act specifically identified RISC-V as one of the next-generation technologies that should receive particular investment focus to preserve and strengthen research and innovation in the EU.
2. Modular, scalable, and customizable. Before RISC-V, companies bought off-the-shelf chips for most applications because it was too expensive and time-consuming to custom-design and build them. This meant that often the chips had more features than were necessary, which could degrade performance (imagine driving a sports car only in third gear). RISC-V’s most basic version consists of just 47 instructions, but RISC-V offers extensions that make it possible to add additional features, such as vector math, for running AI algorithms. Its reduced instruction set simplifies the design process, making it easier and faster to develop chips, and its modular nature allows designers to customize the instruction set based on specific application requirements, optimizing performance and power consumption.
Its scalability makes it suitable for a wide range of computing systems, from simpler devices (e.g., earbuds and sensors) to supercomputers. The modular nature of the architecture allows for easy integration of multiple cores and accelerators, enabling efficient parallel processing and distributed computing. This scalability and customization capabilities make RISC-V a versatile choice for High-Performance Computing (HPC) applications.
3. Energy Efficient. The modular nature of RISC-V allows for a reduced instruction set that can improve performance and is more energy-efficient. By simplifying the instruction set, RISC-V processors can execute instructions more quickly, reducing power consumption and improving performance per watt, which benefits applications ranging from small devices to HPC. Furthermore, its open nature allows for improved power optimization techniques to be developed and shared, so the architecture benefits from collective expertise in power management and energy-efficient design methodologies.
4. Future-Proof. The rate of change in technology is only increasing, which means adaptability is critical for longer-term success. RISC-V’s open standard and modular nature make it more adaptable than current proprietary alternatives. Its collaborative ecosystem enables rapid innovation and quick adoption of new features and advancements. Its architectural flexibility and extensibility allow seamless integration of emerging technologies, such as artificial intelligence and specialized hardware, for data-intensive workloads.
Here are just a few meaningful recent events in the RISC-V ecosystem:
- February 2022 - Intel (INTC) pledged $1 billion to develop the RISC-V ecosystem.
- October 2022 - Google announced a new open-source OS for RISC-V chips.
- December 2022 - Ventana Systems announced its Veyron chip, “the world’s first data center-class RISC-V CPU,” at the RISC-V Summit, and so far, the reviews have been solid.
- December 2022 - Google announced official Android support for RISC-V at the RISC-V Summit during the keynote given by Lars Bergstrom, Google Director of Engineering.
- May 2023 - The RISC-V Software Ecosystem (RISE) project was announced. Its governing board includes Andes Technology (TWSE:6533), Google, Intel, NVIDIA, Qualcomm, Rivos, Samsung (SSNLF), SiFive, T-Head, and Ventana.
- June 2023 - First European RISC-V summit held in Barcelona.
- June 2023 - The first laptop with a RISC-V chip, the Roma by Xcalibyte and DeepComputing, was available for pre-order.
The Bottom Line
The emergence of RISC-V poses a significant challenge to established players in the microchip industry and is a potential game-changer. As of the end of 2022, there were over 10 billion RISC-V cores in the market, and tens of thousands of engineers were working on RISC-V initiatives worldwide. The research firm Semico predicts that the number of chips that include at least some RISC-V technology will grow over 70% annually through 2027. Its open-source nature that fosters collaboration and innovation, customization capabilities, scalability, energy efficiency, agility, and future-proof design make it an ideal choice for a wide range of applications that could redefine market standards.
The views and opinions expressed herein are the views and opinions of the author and do not necessarily reflect those of Nasdaq, Inc.
Lenore Elle Hawkins
Lenore Elle Hawkins has, for over a decade, served as a founding partner of Calit Advisors, a boutique advisory firm specializing in mergers and acquisitions, private capital raise, and corporate finance with offices in Italy, Ireland, and California. She has previously served as the Chief Macro Strategist for Tematica Research, which primarily develops indices for Exchange Traded Products, co-authored the book Cocktail Investing, and is a regular guest on a variety of national and international investing-oriented television programs. She holds a degree in Mathematics and Economics from Claremont McKenna College, an MBA in Finance from the Anderson School at UCLA and is a member of the Mont Pelerin Society.
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