Edit Symbol List
Enter up to 25 symbols separated by commas or spaces in the text box below. These symbols will be available during your session for use on applicable pages.
Don't know the stock symbol? Use the
Symbol Lookup tool.
Alphabetize the sort order of my symbols
Investing just got easier…
Sign up now to become a NASDAQ.com member and begin receiving instant notifications when key events occur that affect the stocks you follow.Access Now
F1Q11 Earnings Call
February 16, 2011 5:00 pm ET
Aart de Geus - Co-Founder, Chairman and Chief Executive Officer
Lisa Ewbank - VP, IR
Brian Beattie - Chief Financial Officer
Paul Thomas - Roth Capital Partners LLC
Thomas Diffely - D.A. Davidson & Co.
Richard Valera - Needham & Company, LLC
Previous Statements by SNPS
» Synopsys Q2 2010 Earnings Call Transcript
» Synopsys, Inc. F1Q10 (Qtr End 01/31/10) Earnings Call Transcript
» Synopsys Inc. F4Q09 (Qtr End 10/31/09) Earnings Call Transcript
Thank you, Beth. Good afternoon, everyone. With us today are Aart de Geus, Chairman and CEO of Synopsys; and Brian Beattie, Chief Financial Officer.
During the course of this conference call, Synopsys will discuss forecasts and targets and will make other forward-looking statements regarding the company and its financial results. While these statements represent our best current judgment about future results and performance as of today, our actual results and performance are subject to many risks and uncertainties that could cause actual results to differ materially from what we expect.
In addition to any risks that we highlight during this call, important factors that may affect our future results are described in our annual report on Form 10-K for the fiscal quarter ended October 31, 2010, and in our earnings release for the first quarter of fiscal year 2011 issued earlier today.
In addition, all financial information to be discussed on this conference call as well as the reconciliation of the non-GAAP financial measures to their most directly comparable GAAP financial measures and supplemental financial information can be found in the current report on Form 8-K that we filed today, our first quarter earnings release and our financial supplement. All of these items are currently available on our website at www.synopsys.com.
With that, I'll turn the call over to Aart de Geus.
Aart de Geus
Good afternoon. I'm happy to report that we started off fiscal 2011 with a strong first quarter, putting us well on track towards meeting our objectives for the year. This is all the more promising against the backdrop of a healthy semiconductor industry. Because Synopsys benefits from a clear industry leadership position, we continue to drive state-of-the-art technology in traditional EDA, and we have achieved a meaningful scale in high-growth adjacencies, such as IP.
From a financial perspective, we delivered revenue of $364.6 million and non-GAAP earnings per share of $0.44. The run rate of the underlying business grew and the outlook for Q2 looks promising. Brian will give you more details in a minute, but let me first make some comments on the current customer landscape.
Overall, our customers communicate a healthy outlook. This confidence is visible in the increased capital expenditures by all the large foundries and IDM, as well as an exciting end market. The wave of new products continues across the board, from consumer goods, such as tablets and smartphones, to new offerings in the industrial, automotive, communication and networking domains. Simply stated, we have entered the age of smart everything, and electronics will become still more pervasive, offering good growth opportunities for Synopsys.
The quest for leading edge silicon to drive advanced products is also visible in the urgency with which our leading customers are driving to new process nodes. 32/28 nanometer designs are ramping quickly, and 22-, 20-nanometer and below developments are in full swing. The complexity and cost of these efforts translate into continued opportunity for Synopsys as they require both advanced EDA and IP.
Against this backdrop, our stated growth objective for the next few years aims at achieving annual high-single digit earnings per share growth. We plan to achieve our objective with five strategies: one, drive organic revenue growth in the low- to mid-single digits for our traditional EDA products; two, achieve double-digit organic growth in our IP and systems adjacencies; three, continue to explore M&A opportunities that broaden our total available market; four, focus on corporate efficiency and allocate resources towards the growing segments in our market; and five, maintain a roughly flat diluted share count of around 151 million shares. In Q1, we executed well on all strategy, and we are well on the way towards our EPS objective for the year.
Let me briefly share some highlights starting with the traditional EDA part of our business. In Q1, we saw a strong demand for our products. Both our contract renewals and a number of incremental sales led to positive growth of our business run rate. Specifically, adoption of our physical implementation solution around IC Compiler is growing with yet another customer deciding to migrate to us after having experienced difficulty in achieving closure with competitive tools. We also made excellent progress with a top graphics company moving to Synopsys for its next advanced chip design.
Overall, we continue to deliver very well from a technology point of view. The summary of our physical design solution achieved a 50% runtime improvement for IC Compiler while adding a powerful new optimization technique for large hierarchical designs. We delivered significant advances in analog simulation, including multicore features, resulting in notable performance improvements. The upcoming DCS simulator release is designed to deliver an amazing 2x speed up in runtime.
And in manufacturing, we shipped a new release of Yield Explorer, which achieved higher productivity by being tightly integrated with our physical design solution. In custom design, we continue to see gradual adoption. One European customer selected Synopsys for both simulation and design after a significant competitive evaluation, and another technology leader chose us for the development of IP for their 20-nanometer process node. Finally, IC Validator, our integrated physical verification solution, continues its customer base expansion with qualification for TSMC 40- and 65-nanometer processes and excellent adoption by customers.